1. Field of the Invention
The invention relates to computer-aided wiring diagram verifying method, program, and apparatus for forming diagram data for a wiring mask from layout data of a circuit design of a large scale semiconductor integrated circuit or the like and, more particularly, to wiring diagram verifying method, program, and apparatus for forming diagram data for a wiring mask including oblique wirings and via cells which are arranged on the oblique wirings from layout data and verifying the diagram data.
2. Description of the Related Arts
Hitherto, in computer-aided designing work of a large scale semiconductor integrated circuit, arrangement of elements is determined on the integrated circuit in accordance with a logic circuit diagram or an electronic circuit diagram called an arrangement wiring design or layout design and after wiring paths among those elements are decided, there is a diagram forming step of forming a mask based on them.
As is well known, layout verification is made in the layout design. The layout verification is made to confirm correctness of the design with respect to diagram forming data (art work data) for mask creation at the last stage of the design.
In the layout Verification, verification called a design rule check (DRC) is made. It is a step of verifying whether the diagram forming data violates a geometrical design rule, that is, a design rule which is designed in consideration of various limitations obtained by examining a manufacturing process or not.
In the conventional design check, whether the data violates the design rule or not is verified by checking an interval between the wiring diagrams on the basis of the design rule. Whether an interval between the wiring diagram and a via diagram, the via diagram, and the wiring diagram satisfy an overlap of them or not is verified so that a contact area after manufacturing can be guaranteed on the basis of the design rule.
Those methods are classical techniques and their general examples are shown in FIGS. 1A and 1B. In the conventional layout verification, first, as shown in FIG. 1A, wirings 300 and 302 of a wiring layer are drawn on the same layer as that of via cells 304 and 306 of a via cell layer on the basis of the layout data. If the wiring 300 and the via cell 304 overlap and the wiring 302 and the via cell 306 overlap by the drawing, respectively, as shown in FIG. 1B, they are automatically blended to be one diagram and metal wiring diagrams 308 and 310 are formed.
As shown in FIG. 1A, the via cells 304 and 306 have forms such that via mats 316 and 318 are coupled with vias 312 and 314, respectively. Wiring overlaps are formed around the vias 312 and 314 by the via mats 316 and 318. With respect to the wiring overlaps, the via mats 316 and 318 are prepared so that contact areas of the wirings 300 and 302 and the vias 312 and 314 have sizes which satisfy wiring overlap values which are held on the basis of the design rule.
Therefore, the via cells 304 and 306 constructed by the vias 312 and 314 and the via mats 316 and 318 become the metal wiring diagrams 308 and 310 as shown in FIG. 1B because the via mats 316 and 318 are blended with the wirings 300 and 302 by a blending process with the wirings 300 and 302.
Subsequently, whether the metal wiring diagrams 308 and 310 satisfy an allowable minimum interval value S between the wiring diagrams based on the geometrical design rule or not is verified. That is, an interval between the metal wiring diagrams 308 and 310 is scanned and since it becomes the minimum in a blended portion of the via cells at intervals 320 and 322, if the intervals 320 and 322 are equal to or larger than the allowable minimum interval value S, it is determined that the design rule is satisfied. If they are smaller than the allowable minimum interval value S, it is determined that an error has occurred. Generally, the allowable minimum interval value S between the wiring diagrams based on the design rule varies in accordance with wiring widths.
Further, also with respect to overlap values 326 and 328 of the vias 312 and 314 in the metal wiring diagrams 308 and 310, verification regarding whether allowable overlap values based on the design rule are satisfied or not is made. Generally, the allowable overlap values also vary in accordance with line widths of the wirings 300 and 302 where the vias 312 and 314 exist. (Refer to JP-A-11-297831, the Official Gazette of Japanese Patent No. 2953051, and the Official Gazette of Japanese Patent No. 2580772.)
Although a wiring pattern is arranged in the horizontal and vertical directions in the conventional layout design, in recent years, in order to shorten a wiring length, reduce a line resistance and a floating capacity, and improve transmitting characteristics accompanied by the realization of a high frequency, an oblique wiring such that the wiring pattern is arranged in the oblique direction of 45° is used. However, in the layout verification regarding the oblique wiring as a target, there are the following problems.
FIG. 2 is an explanatory diagram of the design rule check regarding the oblique wiring as a target. In such a design rule check, oblique wirings 402 and 404 of an oblique wiring layer 400 and via cells 408 and 410 of a via mat layer 406 are fetched as those on the same layer and drawn by an automatic blending process 412, thereby forming blended oblique wiring diagrams 416 and 418 onto a blended diagram layer 414.
Also in this case, the via cells 408 and 410 are constructed by vias 420 and 422 and via mats 424 and 426 and portions of the via mats 424 and 426 are blended with the oblique wirings 402 and 404.
With respect to the blended oblique wiring diagrams 416 and 418, as enlargedly shown in FIG. 3, whether an interval 425 of the oblique wiring portion satisfies the allowable minimum interval value S between the wiring diagrams based on the design rule or not is verified. If it is smaller than the allowable minimum interval value S, it is determined that an error has occurred.
However, in the blended oblique wiring diagrams 416 and 418, projecting portions 427, 428, 430, and 432 are caused in the direction which perpendicularly crosses the oblique wirings due to the blending of the via mats arranged around the vias 420 and 422 so as to have overlap values.
With respect to the projecting portions 427, 428, 430, and 432, if projection amounts lie within a range of manufacturing errors, vertices are rounded at the time of manufacturing. Therefore, with respect to the verification of an interval 434 between the projecting portion 428 of the blended oblique wiring diagram 416 and the blended oblique wiring diagram 418 and an interval 436 between the projecting portion 430 of the blended oblique wiring diagram 418 and the blended oblique wiring diagram 416, an allowable minimum interval value T smaller than the allowable minimum interval value S between the oblique wirings is set.
However, in the design rule check, in the case where the verification of the allowable minimum interval value S between the oblique wirings is executed on the basis of the design rule, with respect to the intervals 434 and 436 of the projecting portions 428 and 430 from the wiring width, although the allowable minimum interval value T regarding the projecting portions is satisfied, the allowable minimum interval value S between the oblique wirings larger than the value T is not satisfied. The diagram forming data violates the design rule, so that a pseudo error occurs.
Therefore, if the projecting portions due to the blending of the via cells exist in the verification of the interval between the oblique wirings, the pseudo error occurs and the intervals cannot be correctly verified.
To avoid such a pseudo error, also with respect to the projecting portions which satisfy the allowable minimum interval value T, the intervals have to be widened so as to have the allowable minimum interval value S between the oblique wirings. To arrange them so as to eliminate all violations in the design rule check, an interval between the oblique wirings larger than needed is required.
An increase in wiring interval due to it results in an increase in wiring length and an increase in area of a chip. Various benefits such as saving of the wiring length owing to the oblique wirings, reduction of wiring delay, improvement of a yield owing to the decrease in chip area, and the like cannot be obtained.